Description

Revision Standard – Active – Draft.The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.

Product Details

ISBN(s):

9781504497176

Number of Pages:

1354

File Size:

1 file , 6 MB

Product Code(s):

STDUD26159

Note:

This product is unavailable in Russia, Belarus